Technical Field
The subject matter of this application relates to microelectronic packages and assemblies in which a plurality of microelectronic elements, e.g., semiconductor chips are arranged in a stacked relation with one another, and may be coupled to an underlying circuit panel, and more specifically to such assemblies having memory storage array chips which may be in a flyby signaling arrangement with one another.
Description of the Related Art
Semiconductor die or chips are flat bodies with contacts of the chip disposed on their front surfaces which are connected to the internal electrical circuitry including active devices of the chip itself. Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer, e.g., server or user computer, or a mobile device such as a smartphone or tablet, for example.
In order to save space certain conventional designs have stacked multiple microelectronic elements or semiconductor chips within a package. This allows the package to occupy a surface area on a substrate that is less than the total surface area of the chips in the stack. However, conventional stacked packages have disadvantages of complexity, cost, thickness and testability and area of an underlying board occupied thereby.
In spite of the above advances, there remains a need for improved stacked packages and especially stacked chip packages and stacked chip assemblies which incorporate a plurality of chips for types of memory such as, for example, dynamic random access memory (DRAM) or flash memory.